Instruction Set Architectures for Quantum Processing Units

摘要

Progress in quantum computing hardware raises questions about how thesedevices can be controlled, programmed, and integrated with existingcomputational workflows. We briefly describe several prominent quantumcomputational models, their associated quantum processing units (QPUs), and theadoption of these devices as accelerators within high-performance computingsystems. Emphasizing the interface to the QPU, we analyze instruction setarchitectures based on reduced and complex instruction sets, i.e., RISC andCISC architectures. We clarify the role of conventional constraints on memoryaddressing and instruction widths within the quantum computing context.Finally, we examine existing quantum computing platforms, including the D-Wave2000Q and IBM Quantum Experience, within the context of future ISA developmentand HPC needs.